Electrical current that is not supposed to flow off in an electronic circuit is called leak current. Leak current increases power consumption and heat in a circuit to become a cause of deterioration of the circuit performance. In light of this, it is important to estimate leak current accurately at circuit design and take a countermeasure.
Due to recent miniaturization of process dimension, the effect of variation caused by the process on the leak current is growing. To deal with this situation, statistical leak analysis that aims to estimate leak current more accurately is known.
Generally, according to the statistical leak analysis, a variation model is created for leak current in cells of a circuit. The variation model is expressed, for example, as an approximation formula having parameters such as gate length, gate width, and threshold voltage (Vth), which can be causes of the variation. The leak current of a circuit is modeled as the sum of variation models for each cell.
With a general-purpose circuit analysis program such as Simulation Program with Integrated Circuit Emphasis (SPICE), the modeled leak current is analyzed. In this way, a yield distribution for leak current of a circuit is calculated. See, for example, Japanese Laid-Open Patent Publication No. 2005-19524 and Japanese Laid-Open Patent Application Publication No. 2003-23078.
However, it is difficult for the statistical leak analysis to create a variation model taking into account of all causes of the variation arising from the process. Even a SPICE model includes an error. Therefore, according to the conventional statistical leak analysis, there is an error (difference) between a calculated yield distribution of leak current and an actually measured yield distribution of leak current. As a result, forced to return to a previous step in a circuit design, a designer bears more workload, thereby prolonging the design period.